The Metrics Simulator A modern, fully featured and performant SystemVerilog Simulator A New Simulator Fully Featured SystemVerilog LRM CompliantGate-level timing and SDF Modern Modern architecture: LLVM-basedCompetitive performance with EDA vendors Advanced Verification Faster Verification using advanced capabilities UVMConstraint solverSystemVerilog assertions (SVA)Code and functional coverage Ready to Integrate Reuse Existing Components PLI and DPI support IEEE 1735 Encryption Simulate encrypted IP from FPGA vendorsEncrypt your own code In Beta VHDL 1076-2019 support