The Metrics Simulator
A modern, fully featured and performant SystemVerilog Simulator
A New Simulator
Fully Featured
- SystemVerilog LRM Compliant
- Gate-level timing and SDF
Modern
- Modern architecture: LLVM-based
- Competitive performance with EDA vendors
Advanced Verification
Faster Verification using advanced capabilities
- UVM
- Constraint solver
- SystemVerilog assertions (SVA)
- Code and functional coverage
Ready to Integrate
Reuse Existing Components
- PLI and DPI support
IEEE 1735 Encryption
- Simulate encrypted IP from FPGA vendors
- Encrypt your own code
Coming Soon
- VHDL 1076-2019 support
Metrics would like to Introduce you to its customer experience (CX) team.
This highly experienced team of experts are here to help ensure you have a great experience with the Metrics Cloud Platform. They will work with you from evaluation to production to make sure you are successful. To get started simply click “Talk To An Expert”, complete the form and one of our engineers will contact you.
Recognized ASIC Verification veteran with expert knowledge in UVM and other constrained random and coverage driven verification methodologies who enjoys solving the most challenging verification problems. Deployed methodology solutions to solve design verification challenges across numerous industry segments, e.g., telecommunication, networking, SoC, graphics, memory, encryption and automotive.
Engineering and Management Professional over 20 years of work experience with a proven track record of successful execution of Design and Verification projects. Extensive experience in defining Multi-Million Gate design verification architectures with UVM based IP , Block and SoC level Hybrid environments.
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