The Metrics Simulator

A modern, fully featured and performant SystemVerilog Simulator

A New Simulator

Fully Featured
  • SystemVerilog LRM Compliant
  • Gate-level timing and SDF
Modern
  • Modern architecture: LLVM-based
  • Competitive performance with EDA vendors

Advanced Verification

Faster Verification using advanced capabilities
  • UVM
  • Constraint solver
  • SystemVerilog assertions (SVA)
  • Code and functional coverage
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Ready to Integrate

Reuse Existing Components
  • PLI and DPI support
IEEE 1735 Encryption
  • Simulate encrypted IP from FPGA vendors
  • Encrypt your own code

Coming Soon

  • VHDL 1076-2019 support