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Over 20 years experience in ASIC design verification. Accomplished ASIC Verification Engineer with experience in both environment and test plan development. Extensive experience in functional testing, system testing, security testing and interoperability testing of software.

Recognized ASIC Verification veteran with expert knowledge in UVM and other constrained random and coverage driven verification methodologies who enjoys solving the most challenging verification problems. Deployed methodology solutions to solve design verification challenges across numerous industry segments, e.g., telecommunication, networking, SoC, graphics, memory, encryption and automotive.

Engineering and Management Professional over 20 years of work experience with a proven track record of successful execution of Design and Verification projects. Extensive experience in defining Multi-Million Gate design verification architectures with UVM based IP , Block and SoC level Hybrid environments.

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